CXMT closes the DRAM process gap with its G5 platform

ChangXin Memory Technologies has put its fifth-generation DRAM platform into mass production, claiming process capability that it says now sits alongside the industry's leading nodes. The Hefei company announced the milestone at the 2026 World Manufacturing Convention on 20 September and used the same stage to show its first two LPDDR5X products built on the platform.

The headline number is an active-area half-pitch of 11.95 nanometres in the memory array, reached with quadruple patterning. CXMT is careful about what that figure means: it is a physical measurement inside the memory array rather than a logic-style process node name, and the company's own small print notes that these measurements carry standard metrology margins of error. Alongside it, the platform reaches a 45:1 capacitor aspect ratio and cuts the core cell array height to 6,762 nanometres using a high-k metal gate process adapted for DRAM.

What the density claim actually says

The commercially interesting number is die density. CXMT says gross die per wafer on G5 is at least 50 per cent higher than on its fourth-generation platform, normalised to an 8Gb density baseline, which it presents as an improvement in power efficiency and cost. That figure counts potential dies cut from a wafer before defective chips are screened out, so it is a statement about how much silicon the process can use rather than a promise about yield. CXMT also reports progress on interface engineering, saddle-fin structures and low-k spacer bitlines, and says it built a digital twin of the development line to model design, tape-out, manufacturing and yield work in software.

The wider context is a memory market that has been short of supply all year. TrendForce put global DRAM industry revenue up 59.5 per cent quarter-on-quarter in the second quarter of 2026, with supply expansion still trailing demand, and the market remains dominated by Samsung, SK hynix and Micron.

The first G5 products are phone memory

Two LPDDR5X parts built on G5 were unveiled at the convention, both with 24Gb per die, a 50 per cent increase over equivalent products from the previous generation. They ship in 496-ball and 245-ball packaging for smartphones and portable electronics, and CXMT says both are already in volume production.

CXMT vice-president Luo Xiaodong told the convention that the new parts have "fully entered" mainstream domestic flagship smartphones, without naming the handset makers or models. "Our process capability is now on par with the most advanced mass-produced nodes in the industry," he said. The company has not published UK or European pricing or availability for any G5 part, and none of the announced products have been independently benchmarked.

Our opinion

Density claims from a memory maker are easy to make and hard to falsify, and the part of this announcement that deserves attention is not the 11.95 nanometre number but the die-per-wafer figure. More dies from the same wafer is what actually moves money in DRAM, because it changes the cost floor on commodity parts that are otherwise interchangeable. CXMT's own footnote is the honest thing here: these are gross dies before screening, which says nothing about how many survive a bin sort at volume.

The strategic picture is the more interesting one. Quadruple patterning is an expensive route to small features, and it is the route a manufacturer takes when it cannot buy the newest lithography. That CXMT is claiming near-parity on a multi-patterning flow tells you how much of the equipment gap can be worked around with process steps and patience, and how much of it is now a question of cost rather than capability. If the G5 platform holds up at scale, the three incumbents face something they have not had in years: a fourth supplier with a credible cost story in the memory that every AI server needs. The claim worth watching next is yield, and CXMT has not published one.