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IonQ runs quantum error correction in real time on one CPU

IonQ has demonstrated the first end-to-end real-time quantum error decoder to run on a single standard CPU, keeping a simulated system at full speed while it fixes errors.

Composed graphic on a dark slate background: the IonQ hexagon mark and wordmark on a logo plate with an orange rule beneath it, above the lines Real-time quantum error decoding and on a single standard CPU, followed by the announcement’s own figures - 408 logical qubits, 88 memory blocks, 31.5m operations and 0.02% decoder stretch under standard noise

Error correction is the unglamorous half of quantum computing. Physical qubits are noisy, so a classical computer has to keep hunting for errors and fixing them while the quantum machine runs, and in most designs that decoding job eventually overwhelms the classical side and forces the quantum computer to wait. IonQ says it has now demonstrated the first end-to-end real-time decoder to run a quantum computer on a single standard, off-the-shelf CPU. The work is described in a preprint posted to arXiv in August and was announced by the company on Tuesday.

What the tests measured

IonQ evaluated its dual-decoder architecture on benchmark circuits simulating up to 408 logical qubits across 88 memory blocks and magic factories, the structures that produce the magic states fault-tolerant machines need. Those circuits ran more than 31.5 million individual quantum operations, a scale IonQ calls MegaQuOp, and under standard operational noise the decoder added as little as 0.02% stretch time, meaning the decoding overhead slowed the computation by almost nothing.

Nicolas Delfosse, paper co-author and quantum research lead at IonQ, said: “Successfully validating real-time decoding across hundreds of logical qubits and over millions of logical operations is an important milestone. Moreover, the fact that our decoder runs on a single CPU provides a practical path to commercial-scale fault-tolerant quantum computing.”

Why one processor matters

The pitch is about classical hardware as much as quantum hardware. IonQ says the result validates a core pillar of its Walking Cat architecture and confirms that the classical overhead does not have to grow exponentially as a system gets wider in logical qubits or deeper in operations, which is the foundation for its roadmap beyond 256 physical qubits towards platforms controlling thousands. John Gamble, vice president at IonQ Architecture, said: “Empirical evidence like this supports our vision for fault tolerance where time-to-solution, cost-to-solution, and energy-to-solution are always our North Star.” IonQ also notes a 2025 result of 99.99% two-qubit gate fidelity, which it describes as a world record.

Our opinion

Quantum companies sell roadmaps in qubit counts, and IonQ has just made a bid to compete on the bill for the boring computer in the corner. That is the right argument to have. A decoder that needs a rack of accelerators to keep up with the qubits is a permanent tax on every application you might ever run, and the energy line in IonQ’s own quote is the tell that the industry knows it. The honest caveat is in the methodology: these numbers come from benchmark circuits simulated to 408 logical qubits rather than a live machine at that width, so the claim to watch is the first hardware run of the same scale. If the single-CPU decoder holds up there, fault tolerance stops being a physics problem and becomes a systems engineering problem, which is a far cheaper kind of problem to have.