Why AI chip packaging is the next silicon bottleneck

For three years the AI race has been measured in transistors and memory bandwidth. TrendForce's latest packaging research argues that the real ceiling has moved somewhere less glamorous: the package. As compute dies and HBM stacks multiply, the silicon interposer that ties them together is running out of room, and the industry has to build outward instead of smaller.

CoWoS-S is running out of interposer

The workhorse has been TSMC's CoWoS-S, which uses a silicon interposer to connect HBM with compute dies, the arrangement that made generative AI accelerators practical. TrendForce says a CoWoS-S package can carry two SoCs or chiplets alongside eight HBM modules, and that manufacturing the interposer is nearing its physical limits as dies grow. It expects CoWoS-S to persist for ASICs such as Microsoft's Maia 200.

Anything larger needs CoWoS-L, which embeds high-speed silicon bridge dies inside the interposer rather than depending on one big piece of silicon. That allows larger reticle-size exposures and tighter integration between compute and memory. Nvidia and AMD AI accelerators already use it, Meta's MTIA 400 is already on it, and AWS and Microsoft are expected to move over in 2027.

The demand pulling it along

TrendForce's forecasts put the pressure in context: Nvidia's high-end GPU shipments are expected to grow around 30% year on year in 2026, AMD begins pushing MI400 and MI450 in the second half of the year, Google leads cloud providers' own silicon on shipment volume with TPU v7, and AWS shifts to Trainium v3 from the second half of 2026. Microsoft and Meta remain more dependent on GPU servers than on their own chips.

That demand is what tightens TSMC's packaging capacity, and the squeeze is why Intel's EMIB is being looked at again. EMIB routes through the package substrate instead of a costly large interposer, and EMIB-T adds through-silicon vias to shorten signal paths, at the cost of routing density. TrendForce expects Google to adopt EMIB-T in 2027 and says AWS is testing EMIB, but still expects CoWoS-L's maturity and yield to keep it the mainstream AI packaging technology through 2028.

Our opinion

Advanced packaging has spent years as a footnote in AI coverage, which is a mistake, because when the reticle limit is the binding constraint the packaging line matters as much as the transistor. Treat the 2028 date as a forecast rather than a roadmap: TrendForce is modelling capacity and yield, not quoting a vendor's plan, and every part of this story depends on TSMC's ability to add packaging capacity faster than demand rises. The more useful signal is the direction of travel. The money is shifting from making chips smaller to making the space around them bigger and cheaper, and that is a race Intel can actually contest.